題目

1. VHDL hazards

(a)

Find all the static hazards in the following circuit.

For earch hazard specify the value of the input variables and which variableis changing when the hazard occus.

紅色的為Static 1 Hazard
當BCD 為 110 時, A 只要改變就會產生 Static 1 Hazard
藍色的為Static 0 Hazard
當BCD 為 000 時, A 只要改變就會產生 Static 0 Hazard

(b)

Design a NAND gate circuit that is free of static hazards to realize the same function.

$F = ((AB)((AC)’+(A’D)’))’$

$F = (AB) + ((AC)(A’D))$

$F = AB + AA’ + AD + A’C + CD$

$F = AB + AD + A’C + CD$

把 Static 1 Hazard 消掉要加上 $BC$

$F = BC + AB + AD + A’C + CD$

用 NAND 表示

$F = ((BC)’(AB)’(AD)’(A’C)’(CD))’ = BC + AB + AD + A’C + CD$

2. VHDL design structure

Describe three different VHDL circuit design structure descriptions and compare them

說明

結構性描述（Structural Description）：這種風格像是電路的藍圖，它詳細說明了電路中各元件如何物理連接起來。適合於需要明確模組化和連接關係的設計，如PCB設計和階層化電路設計。
資料流型式（Data Flow Style）：著重於描述數據在電路中的流動方式，使用布林邏輯來表示訊號間的相互作用。這種風格適合於邏輯相對簡單且以信號處理為主的設計。
行為性描述（Behavioral Description）：從更高的抽象層次描述電路的行為，而不深入具體的物理實現。這使得它特別適合於複雜的電路設計，因為它能夠輕鬆地表達複雜的邏輯和行為。

VHDL有三種主要電路設計描述風格（結構性描述、資料流型式、行為性描述

描述風格	英文名稱	優點	缺點	適用場合	簡述
結構性描述	Structural Description	模組化清楚，連線關係明瞭	較不易理解，繁瑣複雜	階層化設計、PCB設計	描述電路如何通過元件宣告和實例化連接起來，強調模組間的物理連接。
資料流型式	Data Flow Style	布林函數定義明確，設計快速	不易描述複雜的電路	小閘數的電路設計、模組間的分散邏輯	利用布林邏輯函式描述信號之間的關係，強調信號流動和布林代數關係。
行為性描述	Behavioral Description	電路特性之行為性描述清楚明瞭，易於維護	電路合成結果較難控制	大型而複雜的電路模組設計	關注於電路的功能行為，使用較高層次的抽象來描述電路應如何操作。

3. VHDL signel assignment

(a)

Write a selected signal assignment statement to represent the 4 to 1 MUX. Assume that there is an inherent after in the MUX that causes the change in output to occur 10 ns after a change in input.

library iee;
use ieee.std_logic_1164.all;
entity MUX_4_to_1 is port (
    Ap, B, Bp, Phi : in  std_logic;
    C , D          : in  std_logic;
    F              : out std_logic
);
end MUX_4_to_1;

architecture bhr of MUX_4_to_1 is

signal S : std_logic_vector(1 downto 0);

begin

S <= C&D;

with S select
    F <= Ap  after 5 ns when "00",
         B   after 5 ns when "01",
         Bp  after 5 ns when "10",
         Phi after 5 ns when others;

end bhr;

(b)

Repeat (a) using a conditional signel assignment in input.

library iee;
use ieee.std_logic_1164.all;
entity MUX_4_to_1 is port (
    Ap, B, Bp, Phi : in  std_logic;
    C , D          : in  std_logic;
    F              : out std_logic
);
end MUX_4_to_1;

architecture bhr of MUX_4_to_1 is

signal S : std_logic_vector(1 downto 0);

begin

S <= C&D;

  F <= Ap  after 5 ns when S = "00" else
       B   after 5 ns when S = "00" else
       Bp  after 5 ns when S = "00" else
       Phi after 5 ns;

end bhr;

4. Moore sequential

A Moore sequential cirecuit has one input and one output. The output goes to 1 when the input segquence 111 has occured and the output goes to 0 if the input seguence 000 occurs. At all other times the output holds its value.

Derive a Morore state graph and table for the cicuit.

Example

1 2	X = 0 1 0 1 1 1 0 1 0 0 0 1 1 1 0 0 1 0 0 0 Y = 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0

State table

Present State	X = 0	X = 1	Output
S0	S0	S1	0
S1	S0	S2	0
S2	S0	S3	0
S3	S4	S3	1
S4	S5	S3	1
S5	S0	S3	1

5. VHDL concurrent statments

Write a VHDL description of the following combinatinal circuit using concurrent statments.

Each gate has 5 ns after, excludeing the inverter which has a 2 ns after

library iee;
use ieee.std_logic_1164.all;
entity Ans is port (
    A, B, C, D : in  std_logic;
    Z          : out std_logic
);
end Ans;

architecture bhr of Ans is

signal terms : std_logic_vector(5 downto 0);

begin

  terms(0) <= (A and B and C)         after 5 ns;
  terms(1) <= (D and terms(0))        after 5 ns;

  terms(2) <= (B nand C)              after 5 ns;
  terms(3) <= (A and terms(2))        after 5 ns;
  terms(4) <= (not terms(3))          after 2 ns;

  terms(5) <= (terms(1) xor terms(4)) after 5 ns;

  Z <= terms(5);
  
end bhr;

數位系統

題目